1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and more specifically, to a semiconductor device having sidewall insulating films and a method of forming the sidewall insulating films.
2. Description of the Background Art
Conventionally, a sidewall insulating film is known, which is formed for the purpose of insulation on a sidewall of a gate electrode in, for example, an MOS transistor. The sidewall insulating film is formed by anisotropic etching by means of atmospheric plasma etching.
FIGS. 17 to 27 are sectional views for illustrating a manufacturing process of a semiconductor device (an MOS transistor) having a conventional sidewall insulating film. The manufacturing process of the semiconductor device will be described in conjunction with FIGS. 17 to 27.
As in FIG. 17, a gate insulating film 12 formed of a silicon oxide film is formed on a semiconductor substrate 11. After a polycrystalline silicon film 13 is formed by means of chemical vapor deposition, an insulating film 14 formed of a silicon oxide film is formed. A resist layer 15 is formed in a prescribed region on insulating film 14.
As shown in FIG. 18, insulating film 14 and polycrystalline silicon film 13 are anisotropically etched using resist layer 15 as a mask. Anisotropic etching is characterized in that lateral component is sufficiently smaller relative to vertical component as etching proceeds. A conventional plasma etching is known as one among the anisotropic etchings. The plasma etching takes advantage of chemical reactions in the interface between vapor and solid phases to remove unnecessary part of a thin film or a substrate. Among known plasma etching methods, some use CHF.sub.3 /O.sub.2 gas plasma, and others use HBr/Cl.sub.2 gas plasma.
As shown in FIG. 19, impurity ions are implanted into a semiconductor substrate 11 using the patterned polycrystalline silicon film 13 and insulating film 14 as masks, thereby forming a low-concentration impurity region 19.
Now, as in FIG. 20, an insulting film 16 of a silicon oxide film is formed on the entire surface.
As shown in FIG. 21, insulating film 16 is anisotropically etched to form a sidewall insulating film 16a. Impurity ions are implanted into semiconductor substrate 11 using sidewall insulating film 16a and insulating film 14 as masks. A high-concentration impurity region 20 is thus formed. The impurity regions (19, 20) having an LDD (Lightly Doped Drain) structure are thus formed. Polycrystalline silicon film 13 corresponds to a gate electrode in an MOS transistor. In other words, an MOS transistor is formed of polycrystalline silicon film 13 (gate electrode) and the pair of impurity regions (19, 20).
As shown in FIG. 22, a polycrystalline silicon film 17 is formed covering high-concentration impurity region 20, sidewall insulating film 16a and insulating film 14. A resist layer 18 is formed in a prescribed region on polysilicon film 17.
Now, as set forth in FIG. 23, polysilicon film 17 is anisotropically etched by means of plasma etching, using resist film 18 as a mask. The plasma etching performed on polysilicon film 17 is the competitive reaction of etching (protective film removal) and deposition (protective film formation). In other words, a protective film is formed on the surface of polysilicon film 17 at the time of plasma etching. The protective film is removed by ions injected in an approximately vertical direction relative to semiconductor substrate 11. The competitive reaction between such protective film formation and protective film removal causes polycrystalline silicon film 17 to be anisotropically etched (plasma etching).
Now, the principles of forming a sidewall protective film 201a formed at the time of plasma etching will be described. These are disclosed in, for example, in a series of manuscripts prepared for the 34th semiconductor special study seminar held from Jul., 28 to 31, 1990, pp 120-124. FIGS. 28 and 29 are sectional views for illustrating the principles of forming sidewall protective film 201a by plasma etching. A sidewall protective film 201a.sub.1 shown in FIG. 28 originates in resist 18 and a sidewall protective film 201a.sub.2 shown in FIG. 29 originates in etching gas.
Referring to FIG. 28, sidewall protective film 201a.sub.1 is formed of a film of polymer containing carbons. In other words, in the process of plasma etching, besides polycrystalline silicon film 17 is etched, resist 18 is decomposed by the injection of ions formed in plasma. The decomposition of resist 18 causes the reaction product of polymer containing carbons to be deposited on the surfaces of resist 18 and polycrystalline silicon film 17. Among the deposited reaction product, the part of the reaction product formed on the surface 17a of polycrystalline silicon film 17 and the surface 18a of resist 18 is removed by the injection of ions. Sidewall protective film 201a.sub.1 formed on the sidewall 18b of resist 18 and the sidewall 17b of polycrystalline silicon film 17, however, being formed in the direction parallel to the direction of ion injection, is less subject to the impinging ions compared to the surface 17a of polycrystalline silicon film 17. Sidewall protective film 201a.sub.1 will remain on the sidewall 18b of resist 18 and the sidewall 17b of polycrystalline silicon film 17.
Referring to FIG. 29, sidewall protective film 201a.sub.2 originates in etching gas. In other words, an oxide film is formed on the surface 17a and sidewall 17b of polycrystalline silicon film 17, if O.sub.2 is added to polycrystalline silicon film 17, together with Cl.sub.2 which is effective as an etching gas. An oxide film (not shown) is formed on the surface 18a and sidewall 18b of resist 18. The oxide film constitutes sidewall protective film 201a.sub.2. Protective films (not shown) on the surface 17a of polycrystalline silicon film 17 and the surface 18a of resist 18 are removed by ions in a similar manner as shown in FIG. 28.
Sidewall protective films 201a.sub.1 and 201a.sub.2 are thus formed in the part parallel to the direction of ions injected upon plasma etching.
Referring back to FIG. 23, a sidewall protective film 201a is formed on the sidewalls of polycrystalline silicon film 17 and resist 18. Formed on the remaining surface region of polycrystalline silicon film 17 are surface protective films 201d, 201e and a sidewall protective film 201b. A sidewall protective film 201c is formed on the other sidewall (vertical portion) of resist 18. As plasma etching proceeds in this state, surface protecting films 201d and 201e formed in the regions parallel to semiconductor substrate 11 are removed by the injection of ions 30. As the etching further proceeds, the state shown in FIG. 24 is obtained and finally the state shown in FIG. 25 is created. Referring to FIG. 25, a part of sidewall protective film 201a still remains on the sidewalls of polycrystalline silicon film and resist 18. Also, a part of sidewall protective film 201a still remains on the other sidewall (vertical portion) of resist 18. A fence-shaped residue 202 remains on high-concentration impurity region 20 to which polycrystalline silicon film 17 is not connected. FIG. 30 is an enlarged view showing a part of the fence-shaped residue shown in FIG. 25. Referring to FIG. 30, fence-shaped residue 202 is formed of polycrystalline film 17a, and a protective film 201b formed covering polycrystalline silicon film 17a.
After the step shown in FIG. 25, resist 18 (see FIG. 25) is removed as shown in FIG. 26.
An insulating film 61 is formed covering polycrystalline silicon film 17 as shown in FIG. 27. A polycrystalline film 62 is formed in connection with high-concentration impurity region 20. Polycrystalline silicon film 62 constitutes an electrode interconnection layer of an MOS transistor as polycrystalline silicon film 17. This is the way conventional MOS transistors are formed.
In a conventional manner as described above, fence-shaped residue 202 (see FIG. 26) is produced on high-concentration impurity region 20 when anisotropic etching by means of plasma etching is performed onto polycrystalline silicon film 17 which corresponds to an electrode interconnection layer. The formation of polycrystalline silicon film 62 corresponding to the electrode interconnection layer in such a state causes polycrystalline silicon film 62 to be disconnected on the top of fence-shaped residue 202 as shown in FIG. 27. Fence-shaped residue 202 is also hinderance to miniaturization. In other words, polycrystalline silicon film 62 should be formed in a region free form the formation of fence-shaped residue 202. It is also necessary to secure a prescribed contact area between polycrystalline silicon film 62 and high-concentration impurity region 20. The surface area of high-concentration impurity region 20 to be connected to polycrystalline silicon film 62 must be large enough, and, therefore, high-density integration can not be achieved as a result.